//******************************************************************/
//版本说明:
//V0.1		2020-05-02	11:00	yshao	CME测试
//******************************************************************/
//******************************************************************/
//			   全局参数定义
//******************************************************************/

//******************************************************************/
//			   FPGA顶层
//******************************************************************/
module LM901_G01(
		input	wire		sclkin,
		
		input	wire		cmd_mode,
		output	wire		dmx_flag,
		
		input	wire		spi_en,
		input	wire		spi_ck,
		input	wire		spi_mosi,
		output	wire		spi_miso,
		
		output	wire		dmx_ten,
		output	wire		dmx_tx,
		input	wire		dmx_rx,
		
		
		output	wire		sout,

		output	wire		tout
		);

//****************************************************************
//		内部信号
//****************************************************************
wire		resetb, clk16M, sclk_a;
reg		sclk;

reg	[7:0]	us_div;
reg		us_end;
reg	[20:0]	time_us, time_us_a, sync_us;

wire		cmd_d_ok;
wire	[31:0]	cmd_addr;
wire	[7:0]	cmd_data, cmd_rd_d;

reg	[15:0]	count;
wire	[15:0]	dis_tout;

wire		dmx_tx_o, dmx_ten_o;

wire	[7:0]	spi_tout;

//******************************************************************/
//			   参数定义
//******************************************************************/
//程序版本信息
parameter	MAIN_FUNCTION	=  "L";		//ASCII "L"  
parameter	SUB_FUNCTION	=  "M";		//ASCII "M"  
parameter	MAIN_SOLUTION	=  8'd9;	//"9"        
parameter	SUB_SOLUTION	=  8'd1;	//"01"       
parameter	APPLICATION_TYPE=  "G";		//ASCII "G"  
parameter	MAIN_VERSION	=  8'd1;	//"01"       
parameter	SUB_VERSION	=  8'd1;	//"X01"  
parameter	MINI_VERSION	=  8'd18;	//"_3"  

//模块参数设置
defparam        mcu_comm.main_function		=	MAIN_FUNCTION;
defparam        mcu_comm.sub_function		=	SUB_FUNCTION;
defparam        mcu_comm.main_solution		=	MAIN_SOLUTION;
defparam        mcu_comm.sub_solution		=	SUB_SOLUTION;
defparam        mcu_comm.application_type	=	APPLICATION_TYPE;
defparam        mcu_comm.main_version		=	MAIN_VERSION;
defparam        mcu_comm.sub_version		=	SUB_VERSION;
defparam        mcu_comm.mini_version		=	MINI_VERSION;

//**************************************************************
//			内部时钟
//**************************************************************
por_v1_1 u_por(
    .O(resetb)
);

OSC16M u_OSC16M(
		.clkout(clk16M)
		);

wire	sclk_a;

/*
pll_16_150 u_pll_sclk(
		.clkin(clk16M),
		.clkout0(sclk_a),
		.locked()
		);

always @(posedge sclk_a)
	sclk <= ~sclk;
*/

pll_16_75 u_pll_sclk(
		.clkin(clk16M),
		.clkout0(sclk_a),
		.locked()
		);

always @( * )
	sclk <= sclk_a;

always @(posedge sclk)
	if (us_end == 1)
		us_div <= 0;
	else
		us_div <= us_div + 1;
	
always @(posedge sclk)
	if (us_div == 74)//148)
		us_end <= 1;
	else
		us_end <= 0;
	
always @(posedge sclk)
	if (us_end == 1)
		time_us <= time_us + 1;
	
always @(posedge sclk)
	time_us_a <= time_us;
	
always @(posedge sclk)
	sync_us <= time_us ^ time_us_a;
	
//**************************************************************
//			通讯模块
//**************************************************************
L9_spi_com_02 mcu_comm(
		.resetb(resetb),
		.sclk(sclk),
		
		//MCU到FPGA接口	
		.mcu_spi_cs(spi_en),
		.mcu_spi_clk(spi_ck),
		.mcu_spi_mosi(spi_mosi),
		.mcu_spi_miso(spi_miso),

		//MCU设置总线
		.mcu_set_d_ok(cmd_d_ok),
		.mcu_set_addr(cmd_addr[15:0]),
		.mcu_ext_addr(cmd_addr[31:16]),
		.mcu_set_data(cmd_data),
		
		//调试信号
		.tout(spi_tout)
		);


//************************************************************/
//		计数
//************************************************************/

//************************************************************/
//		背板接口
//************************************************************/
display_top_lm display_top_lm(
		//复位&时钟
		.resetb(resetb),
		.sclk(sclk),
		
		.time_us(time_us),
		.sync_us(sync_us),

		//MCU设置接口
	        .set_d_ok(cmd_d_ok),
	        .set_addr(cmd_addr),
	        .set_data(cmd_data),
	        .set_rd_d(cmd_rd_d),
		
		//端口输入输出
		.sout(sout),

		.dmx_tx(dmx_tx_o),
		.dmx_ten(dmx_ten_o),
		.dmx_flag(dmx_flag),
		
		//调试接口
		.tout(dis_tout)
		);

assign	dmx_tx = (cmd_mode == 1)? dmx_tx_o : 1'bz;
assign	dmx_ten = (cmd_mode == 1)? dmx_ten_o : 1'bz;

//************************************************************/
//			调试模块
//************************************************************/
/*
reg		tttt;

debugware_v2_1 u_debug(
//    .trig_out_1(),
//    .data_in_1({7'h0, cmd_d_ok}),
//    .ref_clk_1(sclk),

    .trig_out_0(),
    .data_in_0({dis_tout[7:1], tttt}),
    .ref_clk_0(sclk)
    
);

always	@(posedge sclk)
	tttt <= dis_tout[0] & spi_tout[0];
*/

//************************************************************/
//		调试接口
//************************************************************/                    
always	@(posedge sclk)
	count <= count + 1;
	
//assign	sout = sclkin;//dis_tout[2];
//assign	sout = spi_tout[0];
//assign	sout = cmd_d_ok;
//assign	sout = spi_ck;

//assign	dmx_tx = spi_tout[6];
//assign	dmx_tx = spi_en;
//assign	dmx_ten = 1'b1;
//assign	dmx_tx = (cmd_mode == 1)? spi_en : 1'bz;
//assign	dmx_ten = (cmd_mode == 1)? 1'b1 : 1'bz;

//assign	tout = {cmd_d_ok, cmd_addr[0]};
//assign	tout = {spi_ck, spi_mosi};
//assign	tout = dis_tout[4:3];
//assign	tout = {spi_tout[4], spi_tout[3]};
assign	tout = 0;

endmodule
